Implementation of 8-bit Soft-Core using VHDL

Abstract

In this paper, we have implemented 8 bit soft-core using VHDL, which is compatible with Intel 8051.Design consists of the control block and a memory block communicating through a bi-directional data bus, an address bus, and a few control lines. The control unit fetches instructions from the external memory and executes these instructions to run a program. These instructions are stored in the ROM and decoded by the decoder. The control unit generates the appropriate signal to execute the instruction. With this soft-core we can perform 8 bit data transfer, simple arithmetic & logical operation, branching operation. Also this design support immediate, direct, register, indirect, register indirect addressing modes. In this design part, the codes for the 8051 components like ALU (Arithmetic and Logic Unit), shift register, comparator, etc. have been written in VHDL (VHSIC Hardware Description Language) where VHSIC stands for Very High Speed Integrated Circuit. These individual components together form 8051. In the simulation part, the codes have been tested and verified using Xilinx ISE 8.2i synthesis tool. The waveforms of some of the components are also been verified. In the implementation part, the codes have been downloaded as a single 8051 unit on the SPARTAN 3 FPGA Kit using Xilinx. The components of 8051 like ALU, RAM and ROM have also been downloaded into the FPGA and tested and verified successfully on the kit itself. Today the best way to synthesize ASIC and FPGA devices is VHDL. Synthesis is a process of automatic conversion of a higher level of abstraction to lower level of abstraction. There are several tools available currently. In our project, we have used the commercially available Xilinx ISE 8.2i synthesis tool. It converts Register Transfer Level (RTL) description into gate level netlists. Since the FPGA consists of thousands of AND-OR gates, these netlists can be downloaded successfully into the FPGA.