Design and Performance Analysis of Arithmetic Circuits using Hybrid CMOS Logic and GDI Based Full Adder

Abstract

The Full Adder circuit is an important component in many applications such as Digital Signal Processing architecture, microprocessor, and microcontroller and data processing units. Two new designs have been adopted in order to create full adders to obtain low power, reduction in delay and area parameter. Those two new designs are Hybrid CMOS logic style and Gate Diffusion Input Structure (GDI). Then the modified full adders will be inserted in arithmetic circuits such as carry save adder and carry save array multiplier. The designs will be simulated using T-Spice tool to analyse the performance in terms of area, delay, power and Power Delay Product. These designs successfully will operate at low voltages with tremendous signal integrity and driving capability when compared with the conventional full adders.